1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to repairing faulty global column lines in a dynamic random access memory (DRAM).
2. Description of Related Art
In the fabrication of semiconductor memory devices it is common for an array of memory cells to include one or more defects that prevent proper performance of the memory array. A block diagram of a semiconductor memory array die 100 is shown in FIG. 1, and a simplified schematic of select connections within the die 100 is shown in FIG. 2. The array chosen for illustration is a 16 megabyte dynamic random access memory (DRAM). The memory array is divided into 64 subarrays 105, and each subarray 105 has 512 interleaved columns 110 (shown in FIG. 2) and 512 rows (not visible). The columns 110 run horizontally and extend through each of the eight subarrays 105. The rows each comprise 4 sections running 1/4 of the width of the die 100. Each section has its own driver (not shown), and all 4 row drivers are enabled when the row is selected. Between each subarray 105 and adjacent each subarray 105 bordering an edge of the die 100, there is a sense amplifier gap. The memory array has four input/output (I/O) lines 117 per sense amplifier gap (2 of which are shown in FIG. 2) for reading from and writing to the memory array. To access the memory array, the I/O lines 117 are tied to the columns 110. The columns 110 to be addressed are enabled by a global column line 120 running parallel to the columns 110. The number of columns 110 accessed by each global column line 120 typically equals the number of I/O lines 117 for the subarray 105. In the DRAM of FIG. 1, four cells within a selected subarray 105 may be accessed simultaneously.
The global column lines 120 are driven from the center of the semiconductor die 100 by center logic 125. The global column lines 120 run from the center of the die 100 outward to the edge of the die 100. There are 1024 columns 110 in each quadrant of the die 100, and therefore there are 256 global column lines 120 in each quadrant. In each sense amplifier gap, connections are made between the global column line 120 and gates that connect the columns 110 to the I/O lines 117. A simplified circuit diagram of the connections made in the gap is shown in FIG. 2.
For ease of illustration, FIG. 2 depicts a circuit 200 having two I/O lines 117, instead of the four I/O lines described in reference to FIG. 1. Accordingly, each global column line 120 addresses two columns 110. A circuit having 4 I/O lines 117 is more complex and may have additional space saving features such as column interleaving and sense amp sharing. In FIG. 2, a column 110 is represented by cooperating digit and digit* 210, 220 lines (where an asterisk, "*", is used to indicate a compliment signal). A row is represented by the word line 230. A memory cell 240, consisting of a capacitor 242 and a transistor 244, is connected to the digit* line 220. Typically, memory cells 240 in adjacent rows are alternately connected to either the digit or digit* line 210, 220.
Initially, the digit and digit* lines 210, 220 are equilibrated to a common voltage such as half of a supply voltage, Vcc. When the memory cell 240 is read, the wordline 230 energizes the gate of the transistor 244. If the capacitor 242 is uncharged (i.e. 0 volts corresponding to a logic 0), it will pull down the voltage on the digit* line 220. If the capacitor 242 is charged (i.e. Vcc=3.3 volts corresponding to a logic 1), it will pull up the voltage on the digit* line 220. A sense amplifier 250 senses a voltage difference between the digit and digit* lines 210, 220. The sense amp 250 ties the digit or digit* line 210, 220 attached to the memory cell 240 high or low depending on the logic level read from the memory cell and ties the complimentary digit or digit* line 210, 220 to the opposite logic level. The digit and digit* lines are equilibrated to half of the supply voltage, Vcc at some time after the memory read has been completed.
The digit and digit* lines 210, 220 are connected to the I/O lines 117 through pass gates 260. The global column line 120 is attached to a control input of the pass gates 260. When the global column line 120 is energized, the n-channel transistors, which make up the pass gates 260, are enabled, thus tying the digit and digit* lines 210, 220 to the I/O lines 117.
DRAMs are typically provided with redundancy repair circuits to substitute redundant columns for faulted columns to increase the yield. In the process of repairing a faulted column, the address of the faulted column is remapped to a redundant column. In a memory array having global column lines 120, a single defective column 110 results in all four grouped columns 110 being remapped. The center logic 125 typically includes an inverter that drives the global column line 120 high (Vcc) if a column 110 in the set is selected, and drives the global column line 120 low (GND) if no columns 110 in the set are selected. Grounding the global column line 120 prevents the pass gates 160 from being enabled, thus isolating the associated columns 110 from the I/O lines 117. Because the replaced columns 110 were remapped, they cannot be selected. Accordingly, the center logic 125 always drives the global column line low.
Typically, global column lines 120 are formed on the semiconductor die 100 above the columns 110 with at least one dielectric layer disposed therebetween. For each connection made in the gap, a contact opening must be made in the dielectric layer separating the global column line 120 from the pass gates 260. There is a potential for faults to be formed in the global column line 120 during manufacture. Global column line faults are most likely to occur in the gap regions where the connections to the underlying circuit elements are made.
The lead end of the global column line 120 is grounded due to the low signal provided by the center logic 125, thus preventing the pass gates 260 from being activated. However, if the fault results in an open circuit in the global column line 120, such as a fault caused by an open via, the portion of the global column line 120 between the center logic 125 and the fault is grounded, but the portion between the fault and the distal end of the global column line is floating. Signals present on circuit elements below the floating portion can, through capacitive coupling, transfer a voltage to the floating portion of the faulted global column line 120. If the transferred voltage exceeds the turn-on voltage of the pass gates 260, the pass gates 260 will connect column lines 110 from the disabled columns to the I/O lines 117, resulting in erroneous data being placed on the I/O lines 117. This condition, known as a block fail, results in the semiconductor die 100 being discarded.
It would be desirable to repair a faulted global column line in a manner that prevents block fails due to capacitive coupling between the floating portion of the global column line 120 and the underlying circuit elements.